Particular embodiments generally relate to electronic design automation (EDA) tools and more specifically to clock tree synthesis. A clock tree distributes a clock signal from a source node to a set of sink nodes within an integrated circuit design. The clock tree may include a number of levels of clock tree repeaters that fan the clock signal out to different sink pins. The primary objective in clock tree design is to ensure that the clock signal arrives at all of the sink pins at the same time. The skew in a clock tree is the maximum difference in the arrival time of the clock signal at the sink pins. A clock tree synthesis (CTS) tool is used to generate a clock tree with good clock skew.